The use of phase comparators is commonplace in the processing of received signals in communications systems, typically forming part of phase locked loops in clock recovery circuits and frequency synthesizer circuits. Analog phase comparators are well established and are both fast and accurate. For certain applications however, analog phase detectors cannot be utilised since, for example, they cannot directly derive phase information from signals of different frequencies without first dividing the signals to a common frequency.
The output of analog phase detectors is also not suitable for directly driving digital circuits. Consequently, all-digital phase comparators have been utilised in circuits requiring subsequent digital signal processing, as for example disclosed in U.S. Pat. No. 4,504,799.
A commonly used form of digital phase comparator effects comparison of phase by counting over a predetermined time period a number of pulses for a signal under test and comparing it with a count for the same period of pulses of a reference signal, such as derived from a stable clock. A disadvantage of this technique, as discussed in U.S. Pat. No. 5,084,669, is that it provides limited resolution since the count is based on integral numbers of pulses and also there is a trade off between the response time and accuracy because, in order to improve accuracy, the predetermined time period must be extended.
It is also known from U.S. Pat. No. 5,519,343 to utilise a phase accumulator to synthesise a desired frequency by adding at each cycle of a clock signal a phase value to an accumulator value which is reset to zero when the accumulated value reaches a maximum value, one cycle of the output frequency being generated at each reset.